package sph_pkg;

// `define RVP
`define M2
// `define GO_BIG

parameter 		TRUE 	= 1'b1,
				FALSE 	= 1'b0,
				HIGHZ	= 1'bz,
				HIGH		= 1'b1,
				LOW		= 1'b0;
parameter OOB_SPEC_REVISION = 16'h00_07;

`ifdef M2
	parameter   	FPGA_REVISION 	= 16'h00_11;        // FPGA verion, Always odd number for M2
	parameter 		BOARD_ID  = 8'h26; 					// M2
`elsif GO_BIG
	parameter   	FPGA_REVISION 	= 16'h05_0A;		// FPGA version, 5.x and above for GO_BIG
	parameter 		BOARD_ID  = 8'h27; 					// GO_BIG RVP Fab-2 HW, diferent board ID to include a different DDR M/m rounting
`elsif RVP
	parameter   	FPGA_REVISION 	= 16'h00_12;        // FPGA verion, Always even number for RVP
	parameter 		BOARD_ID  = 8'h25; 					// RVP
`else
	parameter   	FPGA_REVISION 	= 16'h00_08;        // FPGA verion, Always even number for RVP
`endif

parameter   	I2C_SLAVE_ADDR 		= 7'h6A;        // 7-bit slave address; 8th bit = R/W#
parameter   	FRU_SLAVE_ADDR 		= 7'h53;        // 7-bit slave address; 8th bit = R/W#
parameter		I2C_SLAVE_ADDR_BIOS		= 7'h16; 		// BIOS is currently happy with this address.
parameter   	I2C_PROXY_SPEED 		= 1'b1;         // 0 = 100kHz ; 1 = 1MHz
parameter   	UART_BASE_ADDR 		= 16'h03f8;     // 16550 COM1 - [3:0] used for internal register addressing

// parameter BUAD_RATE_ONE_CHAR	= 14'd4774; // TODO: 115200 = d4774, change to d9548 for 57600
parameter BUAD_RATE_ONE_CHAR	= 14'd9548;


parameter 		AVMM_L0_ERROR_REG_SIZE 		= 8;
parameter		ESPI_AVMM_REG_SIZE			= 4; //Bytes

typedef struct packed{
	logic [7:0] byte1;
	logic [7:0] byte2;
	logic [1:0] rsrvd1;
	logic FLASH_NP_AVAIL;
	logic FLASH_C_AVAIL;
	logic [1:0] rsrvd2;
	logic FLASH_NP_FREE;
	logic FLASH_C_FREE;
	logic OOB_AVAIL;
	logic VWIRE_AVAIL;
	logic NP_AVAIL;
	logic PC_AVAIL;
	logic OOB_FREE;
	logic VWIRE_FREE;
	logic NP_FREE;
	logic PC_FREE;
	} EspiAVmm_Status_IntCntrlRegType;



typedef struct packed {
	logic [7:0] byte1;
	logic [7:0] byte2;
	logic [3:0] rsrvd1;
	logic CH_3_MLFRMD_Pkt;
	logic CH_2_MLFRMD_Pkt;
	logic CH_1_MLFRMD_Pkt;
	logic CH_0_MLFRMD_Pkt;
	logic [1:0] rsrvd2;
	logic GetWoAvail;
	logic PutWoAvail;
	logic UnExpectedCSRemoval;
	logic CmdPhaseCRCError;
	logic InvalidCycleType;
	logic InvalidCmd;
	} EspiAvmm_ErrorRegType;

typedef struct packed {
	logic Enable;
	logic ModifierEnable;
	logic rsrvd1;
	logic AlertMode;
	logic IOModeSel;
	logic IOModeSupport;
	logic Alert_n_Sel;
	logic [2:0] Freq;
	logic Alert_n_Support;
	logic [2:0] MaxFreqSupport;
	logic [3:0] MaxWaitStateAllowed;
	logic [3:0] rsrvd2;
	logic CH3Supported;
	logic CH2Supported;
	logic CH1Supported;
	logic CH0Supported;
	} EspiAvmm_GenCnfgRegType;





typedef enum logic [7:0] {		CMD_0  					= 8'h00,
							CMD_8  					= 8'h08,
							CMD_32 					= 8'h20,
							CMD_87 					= 8'h57,
							CMD_96 					= 8'h60,
							CMD_104					= 8'h68,
							CMD_112					= 8'h70,
							CMD_122					= 8'h7A,
							CMD_132					= 8'h84,
							COM1_DATA		    			= 8'h85,
							COM1_STATUS				= 8'h86,
							POST_CODE_BUFFER			= 8'h87,
							SPI_CMD_STATUS				= 8'h88,
							SPI_ADDR					= 8'h89,
							SPI_DATA_IN				= 8'h8a,
							SPI_DATA_OUT				= 8'h8b,
							GPIO_CONFIG				= 8'h8c,
							GPIO_OUTPUT				= 8'h8d,
							GPIO_INPUT				= 8'h8e,
							GPIO_ALERT_CNTRL			= 8'h8f,
							GPIO_ALERT_STATUS			= 8'h90,
							STATUS_REGISTER			= 8'h91,
							// AT_SCALE_DBG_STATUS_0 		= 8'h92,
							// AT_SCALE_DBG_STATUS_1 		= 8'h93,
							// AT_SCALE_DBG_DATA			= 8'h94,
							ALERT_CNTRL				= 8'hfd,
							ALERT_STATUS				= 8'hfe,
							DISCOVERY_BLOCK			= 8'hff} wvFBID_AddressEnumType;


parameter		CMD_0_INDX  					= 8'd0,
			CMD_8_INDX  					= 8'd1,
			CMD_32_INDX 					= 8'd2,
			CMD_87_INDX 					= 8'd3,
			CMD_96_INDX 					= 8'd4,
			CMD_104_INDX					= 8'd5,
			CMD_112_INDX					= 8'd6,
			CMD_122_INDX					= 8'd7,
			CMD_128_INDX					= 8'd8,

			COM1_DATA_INDX    				= 8'd9,
			COM1_STATUS_INDX				= 8'd10,

			POST_CODE_BUFFER_INDX			= 8'd11,

			SPI_CMD_STATUS_INDX				= 8'd12,
			SPI_ADDR_INDX					= 8'd13,
			SPI_DATA_IN_INDX				= 8'd14,
			SPI_DATA_OUT_INDX				= 8'd15,

			GPIO_CONFIG_INDX				= 8'd16,
			GPIO_OUTPUT_INDX				= 8'd17,
			GPIO_INPUT_INDX					= 8'd18,
			GPIO_ALERT_CNTRL_INDX			= 8'd19,
			GPIO_ALERT_STATUS_INDX			= 8'd20,

			STATUS_REGISTER_INDX			= 8'd21,

			AT_SCALE_DBG_STATUS_0_INDX 		= 8'd22,
			AT_SCALE_DBG_STATUS_1_INDX 		= 8'd23,
			AT_SCALE_DBG_DATA_INDX			= 8'd24,

			ALERT_CNTRL_INDX				= 8'd25,
			ALERT_STATUS_INDX				= 8'd26,

			DISCOVERY_BLOCK_INDX			= 8'd27;

parameter	FBID_COUNT						= 27;

parameter		CMD_0_SIZE		= 8'd6,
			CMD_8_SIZE		= 8'd22,
			CMD_32_SIZE 		= 8'd53,
			CMD_87_SIZE 		= 8'd7,
			CMD_96_SIZE 		= 8'd7,
			CMD_104_SIZE		= 8'd7,
			CMD_112_SIZE		= 8'd8,
			CMD_122_SIZE		= 8'd8,
			CMD_128_SIZE		= 8'd8;

parameter 	FLASH_SIZE 			= 8'd255;		// Flash Size for isntan

//Register Indices for i2c_status_reg
parameter DIG_THERM_SENSOR      = 8'd0;
parameter MEM_THERM_SENSOR      = 8'd1;
parameter AVG_PWR               = 8'd2;
parameter BIOS_VER              = 8'd3;
parameter PENDING_BIOS_VER      = 8'd4; //Rename to INBAND_WIP
parameter MAX_DIG_THERM_SENSOR  = 8'd5;
parameter BOM_BOARD_ID          = 8'd6;
parameter FAB_ID                = 8'd7;
parameter MODULE_THRM_PWR       = 8'd8;		//TDP
parameter MAX_THRM_THR          = 8'd9;
parameter MIN_THRM_THR          = 8'd10;
parameter FPGA_REV_INDX			= 8'd11;
parameter SCRATCH_REG_INDX		= 8'd12;

parameter STATUS_REG_COUNT 	= 12 ; 		// 0-based count

typedef enum logic[AVMM_L0_ERROR_REG_SIZE-1:0] { 	TimeOutError			= 8'h1,
													Success					= 8'h0} AvalonL0FsmMsgEnum;
typedef enum logic[1:0]  {	READ_REQ 	= 2'b01,
							WRITE_REQ 	= 2'b10,
							INVALID_REQ = 2'b11,
							NO_REQ		= 2'b00} AVMMAccessTypeEnum;

typedef enum reg { 	READ 	= 1'b1,
					WRITE 	= 1'b0,
					RDWRUNKNOWN = 1'bx,
					RDWRHIGHZ	= 1'bz}Rd1Wr0Enum;


// parameter BOARD_ID          = 8'h27; // PCIE
// parameter BOARD_ID          = 8'h28; // Custom
// parameter BOARD_ID          = 8'h29; // RSVD

parameter BOM_ID	            = 8'h00;
parameter FAB_NUM	            = 8'h00;



endpackage : sph_pkg
